The project for this course was for groups of two students each to develop an Analog to Digital Converter (ADC). An ADC is a circuit that has an analog input within a range given by two other inputs. The output is a digital approximation (the nearest of 16 discrete values) of the input voltage.

The ADC consisted of three components: the clocking circuit, the digital to analog converter (DAC), and the finite state machine (the controller).

The clocking circuit (bottom block) was given to us premade, so that all we had to do was connect the inputs and outputs.

The DAC (the top block) is essencially a digitally-controlled potentiometer whose ends connect to two input pins for the control voltage. The DAC was drawn in manually using transmission gates (two transistors back to back) to make cells, then the cells were assembled together to make up a 4x4 grid. Logic decoders attached to the sides figured out which row and column to activate, essencially picking off one of 16 points along a long resistive strip of polysilicon.

The finite state machine (the middle block) controls the circuit using a successive-approximation algorithm. It compares the input analog voltage to the digitally-controlled DAC output, one bit at a time until the most acurate of the 16 distict values is reached. It then outputs a "ready" signal to let the external equipment know when the digital output is correct.

Implementation of this portion included coding in Verilog, simulating (testing the code), synthesizing (tranlating into logic cells), then testing again. The resulting block of cells, wired up to the other components and external pin pads, produced the final layout which could be tested yet again, before being sent off to be fabricated, two designs per one MOSIS tinychip.

When the physical chips arrived, they were tested for functionality, and found to be in fully working condition. For more detail, view the final technical memo and the testing document (including the test data) or browse through the code, of which the most interesting would likely be the successive-approximation register finite state machine code .

Peter Susi and I worked as partners to develop this project.