h Vdd!
l Gnd!
clock clk 0 0 1 1
vector data m_data_7_ m_data_6_ m_data_5_ m_data_4_ m_data_3_ m_data_2_ m_data_1_ m_data_0_
vector addr m_addr_7_ m_addr_6_ m_addr_5_ m_addr_4_ m_addr_3_ m_addr_2_ m_addr_1_ m_addr_0_
analyzer clk rst tx_cmd col_det car_det data addr shift_out tx_rdy 
h rst
l col_det
l car_det
l tx_cmd
set data 00000101
@ ASM_transmitter.reset
c 2
l rst
c 1
h tx_cmd
c 2
l tx_cmd
c 7
set data 00000011
c 8
set data 00000111
c 8
set data 10101010
c 8
c 8
c 8
set data 11111111
c 20