/* cad5 -- Tue May  6 14:58:59 2003
   Initial dc_shell Variable Values */


__is_in_fpm__ = 1
_bs_arch = "sparcOS5"
_bs_suppress_errors = {"PWR-18", "OPT-931", "OPT-932"}
_bs_valid_program = "true"
acs_area_report_suffix = "area"
acs_bs_exec = ""
acs_bsub_args = "set acs_bsub_args"
acs_bsub_exec = "bsub"
acs_budget_output_file_suffix = "btcl.out"
acs_budget_script_file_suffix = "btcl"
acs_budgeted_cstr_suffix = "con"
acs_compile_script_suffix = "autoscr"
acs_constraint_file_suffix = "con"
acs_cstr_report_suffix = "cstr"
acs_db_suffix = "db"
acs_dc_exec = ""
acs_default_pass_name = "pass"
acs_global_user_compile_strategy_script = "default.compile"
acs_log_file_suffix = "log"
acs_make_args = "set acs_make_args"
acs_make_exec = "gmake"
acs_makefile_name = "Makefile"
acs_num_parallel_jobs = "1"
acs_override_script_suffix = "scr"
acs_qor_report_suffix = "qor"
acs_script_mode = "dcsh"
acs_timing_report_suffix = "tim"
acs_tr_exec = ""
acs_use_default_delays = "false"
acs_use_lsf = "false"
acs_user_budgeting_script = "budget.scr"
acs_user_compile_strategy_script_suffix = "compile"
acs_work_dir = "/home/marstond/tx2"
atpg_bidirect_output_only = "false"
atpg_test_asynchronous_pins = "true"
auto_link_disable = "false"
auto_link_options = "-all"
auto_wire_load_selection = "true"
bc_allow_shared_memories = "false"
bc_chain_read_into_mem = "true"
bc_chain_read_into_oper = "true"
bc_constrain_signal_memories = "false"
bc_detect_array_accesses = "false"
bc_detect_memory_accesses = "false"
bc_enable_analysis_info = "false"
bc_enable_chaining = "true"
bc_enable_multi_cycle = "true"
bc_enable_speculative_execution = "false"
bc_estimate_mux_input = 4
bc_estimate_timing_effort = "high"
bc_fsm_coding_style = "one_hot"
bc_group_eql_logic = "true"
bc_group_index_logic = "true"
bc_infer_multibit = "false"
bc_minimum_multibit_component_width = 4
bc_report_filter = ""
bc_synrtl_map_to_gtech = "true"
bc_synrtl_write_dcsh_and_dctcl = "false"
bc_synrtl_write_precompiled_designware = "false"
bc_synrtl_write_preserved_functions = "false"
bc_time_all_sequential_op_bindings = "false"
bc_use_registerfiles = "false"
bin_path = "/me3/cad/synopsys/2000.05/sparcOS5/syn/bin"
bus_dimension_separator_style = "]["
bus_extraction_style = "%s[%d:%d]"
bus_inference_descending_sort = "true"
bus_inference_style = ""
bus_minus_style = "-%d"
bus_multiple_separator_style = ","
bus_naming_style = "%s[%d]"
bus_range_separator_style = ":"
cache_dir_chmod_octal = "777"
cache_file_chmod_octal = "666"
cache_read = {"~"}
cache_read_info = "false"
cache_write = "~"
cache_write_info = "false"
change_names_dont_change_bus_members = "false"
change_names_update_inst_tree = "true"
check_error_list = {"CMD-004", "CMD-006", "CMD-007", "CMD-008", "CMD-009", "CMD-010", "CMD-011", "CMD-012", "CMD-014", "CMD-015", "CMD-016", "CMD-019", "CMD-026", "CMD-031", "CMD-037", "DB-1", "DCSH-11", "DES-001", "FILE-1", "FILE-2", "FILE-3", "FILE-4", "LINK-5", "LINK-7", "LINT-7", "LINT-20", "LNK-023", "OPT-100", "OPT-101", "OPT-102", "OPT-114", "OPT-124", "OPT-127", "OPT-128", "OPT-155", "OPT-157", "OPT-181", "OPT-462", "UI-11", "UI-14", "UI-15", "UI-16", "UI-17", "UI-19", "UI-20", "UI-21", "UI-22", "UI-23", "UI-40", "UI-41", "UID-4", "UID-6", "UID-7", "UID-8", "UID-9", "UID-13", "UID-14", "UID-15", "UID-19", "UID-20", "UID-25", "UID-27", "UID-28", "UID-29", "UID-30", "UID-32", "UID-58", "UID-87", "UID-103", "UID-109", "UID-270", "UID-272", "UID-403", "UID-440", "UID-444", "UIO-2", "UIO-3", "UIO-4", "UIO-25", "UIO-65", "UIO-66", "UIO-75", "UIO-94", "UIO-95", "EQN-6", "EQN-11", "EQN-15", "EQN-16", "EQN-18", "EQN-20"}
command_log_file = "./command.log"
company = ""
compatibility_version = "2000.05-1"
compile_assume_fully_decoded_three_state_busses = "false"
compile_automatic_clock_phase_inference = "strict"
compile_checkpoint_cpu_interval = 0.000000
compile_checkpoint_filename = "./CHECKPOINT.db"
compile_checkpoint_phases = "false"
compile_checkpoint_pre_area_filename = "./CHECKPOINT_PRE_AREA.db"
compile_checkpoint_pre_delay_filename = "./CHECKPOINT_PRE_DELAY.db"
compile_checkpoint_pre_drc1_filename = "./CHECKPOINT_PRE_DRC1.db"
compile_checkpoint_pre_drc2_filename = "./CHECKPOINT_PRE_DRC2.db"
compile_cpu_limit = 0.000000
compile_create_mux_op_hierarchy = "true"
compile_create_wire_load_table = "false"
compile_dcl_performance_mode = "true"
compile_delete_unloaded_sequential_cells = "true"
compile_disable_hierarchical_inverter_opt = "false"
compile_dont_touch_annotated_cell_during_inplace_opt = "false"
compile_dont_use_dedicated_scanout = 1
compile_dw_simple_mode = "false"
compile_fix_cell_degradation = "false"
compile_hold_reduce_cell_count = "false"
compile_implementation_selection = "true"
compile_instance_name_prefix = "U"
compile_instance_name_suffix = ""
compile_log_format = "  %elap_time %area %wns %tns %drc %endpoint"
compile_mux_no_boundary_optimization = "false"
compile_negative_logic_methodology = "false"
compile_new_boolean_structure = "false"
compile_no_new_cells_at_top_level = "false"
compile_preserve_subdesign_interfaces = "false"
compile_retime_license_behavior = "wait"
compile_sequential_area_recovery = "false"
compile_simple_mode_block_effort = "none"
compile_top_all_paths = "false"
compile_update_annotated_delays_during_inplace_opt = "true"
compile_use_fast_delay_mode = "true"
compile_use_low_timing_effort = "false"
context_check_status = "false"
create_clock_no_input_delay = "false"
current_design = "<<undefined>>"
current_instance = "<<undefined>>"
da_ref_manual = "synth/daptr/toc.pdf"
db2sge_bit_type = "std_logic"
db2sge_bit_vector_type = "std_logic_vector"
db2sge_command = "/me3/cad/synopsys/2000.05/sparcOS5/syn/bin/db2sge"
db2sge_display_instance_names = "false"
db2sge_display_pin_names = "false"
db2sge_display_symbol_names = "false"
db2sge_one_name = "'1'"
db2sge_output_directory = ""
db2sge_overwrite = "true"
db2sge_scale = 2
db2sge_script = "/me3/cad/synopsys/2000.05/admin/setup/.dc_write_sge"
db2sge_target_xp = "false"
db2sge_tcf_package_file = "synopsys_tcf.vhd"
db2sge_unknown_name = "'X'"
db2sge_use_bustaps = "false"
db2sge_use_compound_names = "true"
db2sge_use_lib_section = ""
db2sge_zero_name = "'0'"
dc_shell_mode = "default"
dc_shell_status = 1
default_input_delay = 30.000000
default_name_rules = ""
default_output_delay = 30.000000
default_port_connection_class = "universal"
default_schematic_options = "-size infinite"
design_library_file = ".synopsys_vss.setup"
designer = ""
disable_auto_time_borrow = "false"
disable_library_transition_degradation = "false"
dpcm_arc_sense_mapping = "TRUE"
dpcm_debuglevel = "0"
dpcm_functionscope = "global"
dpcm_level = "performance"
dpcm_libraries = {}
dpcm_rulepath = {}
dpcm_rulespath = {}
dpcm_slewlimit = "TRUE"
dpcm_tablepath = {}
dpcm_temperaturescope = "global"
dpcm_version = "IEEE-P1481"
dpcm_voltagescope = "global"
dpcm_wireloadscope = "global"
duplicate_ports = "false"
dw_prefer_mc_inside = "false"
echo_include_commands = "true"
eco_align_design_verbose = "false"
eco_allow_register_type_difference = "false"
eco_connect_resource_cell_inputs = "true"
eco_correspondence_analysis_verbose = "false"
eco_directives_verbose = "false"
eco_implement_effort_level = "low"
eco_instance_name_prefix = "eco_"
eco_recycle_verbose = "true"
eco_remap_register_verbose = "false"
eco_reuse_verbose = "false"
edifin_autoconnect_offpageconnectors = "false"
edifin_autoconnect_ports = "false"
edifin_dc_script_flag = ""
edifin_delete_empty_cells = "true"
edifin_delete_ripper_cells = "true"
edifin_ground_net_name = ""
edifin_ground_net_property_name = ""
edifin_ground_net_property_value = ""
edifin_ground_port_name = ""
edifin_instance_property_name = ""
edifin_lib_in_osc_symbol = ""
edifin_lib_in_port_symbol = ""
edifin_lib_inout_osc_symbol = ""
edifin_lib_inout_port_symbol = ""
edifin_lib_logic_0_symbol = ""
edifin_lib_logic_1_symbol = ""
edifin_lib_mentor_netcon_symbol = ""
edifin_lib_out_osc_symbol = ""
edifin_lib_out_port_symbol = ""
edifin_lib_ripper_bits_property = ""
edifin_lib_ripper_bus_end = ""
edifin_lib_ripper_cell_name = ""
edifin_lib_ripper_view_name = ""
edifin_lib_route_grid = 1024
edifin_lib_templates = {}
edifin_portinstance_disabled_property_name = ""
edifin_portinstance_disabled_property_value = ""
edifin_portinstance_property_name = ""
edifin_power_net_name = ""
edifin_power_net_property_name = ""
edifin_power_net_property_value = ""
edifin_power_port_name = ""
edifin_use_identifier_in_rename = "false"
edifin_view_identifier_property_name = ""
edifout_dc_script_flag = ""
edifout_design_name = "Synopsys_edif"
edifout_designs_library_name = "DESIGNS"
edifout_display_instance_names = "false"
edifout_display_net_names = "false"
edifout_external = "true"
edifout_external_graphic_view_name = "Graphic_representation"
edifout_external_netlist_view_name = "Netlist_representation"
edifout_external_schematic_view_name = "Schematic_representation"
edifout_ground_name = "logic_0"
edifout_ground_net_name = ""
edifout_ground_net_property_name = ""
edifout_ground_net_property_value = ""
edifout_ground_pin_name = "logic_0_pin"
edifout_ground_port_name = "GND"
edifout_instance_property_name = ""
edifout_instantiate_ports = "false"
edifout_library_graphic_view_name = "Graphic_representation"
edifout_library_netlist_view_name = "Netlist_representation"
edifout_library_schematic_view_name = "Schematic_representation"
edifout_merge_libraries = "false"
edifout_multidimension_arrays = "false"
edifout_name_oscs_different_from_ports = "false"
edifout_name_rippers_same_as_wires = "false"
edifout_netlist_only = "false"
edifout_no_array = "false"
edifout_numerical_array_members = "false"
edifout_pin_direction_in_value = ""
edifout_pin_direction_inout_value = ""
edifout_pin_direction_out_value = ""
edifout_pin_direction_property_name = ""
edifout_pin_name_property_name = ""
edifout_portinstance_disabled_property_name = ""
edifout_portinstance_disabled_property_value = ""
edifout_portinstance_property_name = ""
edifout_power_and_ground_representation = "cell"
edifout_power_name = "logic_1"
edifout_power_net_name = ""
edifout_power_net_property_name = ""
edifout_power_net_property_value = ""
edifout_power_pin_name = "logic_1_pin"
edifout_power_port_name = "VDD"
edifout_skip_port_implementations = "false"
edifout_target_system = ""
edifout_top_level_symbol = "true"
edifout_translate_origin = ""
edifout_unused_property_value = ""
edifout_write_attributes = "false"
edifout_write_constraints = "false"
edifout_write_properties_list = {}
enable_instances_in_report_net = "false"
enable_page_mode = "true"
enable_recovery_removal_arcs = "false"
equationout_and_sign = "*"
equationout_or_sign = "+"
equationout_postfix_negation = "true"
exit_delete_filename_log_file = "true"
filename_log_file = "filenames.log"
find_converts_name_lists = "false"
found_arch_apollo = 0
found_x11_vendor_string_apollo = 0
gen_bussing_exact_implicit = "false"
gen_cell_pin_name_separator = "/"
gen_create_netlist_busses = "true"
gen_dont_show_single_bit_busses = "false"
gen_match_ripper_wire_widths = "false"
gen_max_compound_name_length = 256
gen_max_ports_on_symbol_side = 0
gen_open_name_postfix = ""
gen_open_name_prefix = "Open"
gen_show_created_busses = "false"
gen_show_created_symbols = "false"
gen_single_osc_per_name = "false"
generic_symbol_library = "generic.sdb"
hdl_keep_licenses = "true"
hdl_naming_threshold = 20
hdl_preferred_license = ""
hdlin_advisor_directory = "."
hdlin_auto_save_templates = "FALSE"
hdlin_check_no_latch = "FALSE"
hdlin_dont_check_param_width = "FALSE"
hdlin_dont_infer_mux_for_resource_sharing = "true"
hdlin_dont_turbo_instances_with_generics = "true"
hdlin_enable_analysis_info = "false"
hdlin_enable_analysis_info_for_analyze = "true"
hdlin_enable_rtldrc_info = "false"
hdlin_enable_vpp = "false"
hdlin_ff_always_async_set_reset = "TRUE"
hdlin_ff_always_sync_set_reset = "FALSE"
hdlin_hide_resource_line_numbers = "FALSE"
hdlin_infer_multibit = "default_none"
hdlin_infer_mux = "default"
hdlin_keep_feedback = "FALSE"
hdlin_keep_inv_feedback = "TRUE"
hdlin_latch_always_async_set_reset = "FALSE"
hdlin_merge_nested_conditional_statements = "false"
hdlin_mux_oversize_ratio = 100
hdlin_mux_size_limit = 32
hdlin_preserve_vpp_files = "false"
hdlin_reg_report_length = 60
hdlin_replace_synthetic = "FALSE"
hdlin_report_inferred_modules = "true"
hdlin_translate_off_skip_text = "false"
hdlin_vhdl93_concat = "true"
hdlin_vpp_temporary_directory = ""
hdlin_write_gtech_design_directory = "."
hdlout_internal_busses = "FALSE"
hier_dont_trace_ungroup = 0
hlo_ignore_priorities = "false"
hlo_minimize_tree_delay = "true"
hlo_resource_allocation = "constraint_driven"
hlo_resource_implementation = "use_fastest"
hlo_share_common_subexpressions = "true"
hlo_share_effort = "low"
hlo_transform_constant_multiplication = "false"
init_path = "/me3/cad/synopsys/2000.05/auxx/syn"
insert_dft_clean_up = "true"
insert_test_design_naming_style = "%s_test_%d"
jtag_manufacturer_id = 0
jtag_part_number = 65535
jtag_port_drive_limit = 6
jtag_test_clock_port_naming_style = "jtag_tck%s"
jtag_test_data_in_port_naming_style = "jtag_tdi%s"
jtag_test_data_out_port_naming_style = "jtag_tdo%s"
jtag_test_mode_select_port_naming_style = "jtag_tms%s"
jtag_test_reset_port_naming_style = "jtag_trst%s"
jtag_version_number = 0
lbo_cells_in_regions = "false"
ldd_return_val = "0"
ldd_script = "/me3/cad/synopsys/2000.05/auxx/syn/scripts/list_duplicate_designs.dcsh"
libgen_max_differences = -1
libgen_spdm_extract_enable = "false"
libgen_spdm_extract_ratio = "0.667"
libgen_spdm_extract_sigma = "5.0"
link_force_case = "check_reference"
link_library = {"*", "msu_scmos.db"}
lsiin_net_name_prefix = "NET_"
lsiout_inverter_cell = ""
lsiout_upcase = "false"
ltl_drc_use_center_of_mass = "true"
ltl_enable_mean_physical_port_location = "false"
ltl_lbo_use_all_transforms = "true"
ltl_new_critical_net_fixing_delay = "true"
ltl_new_critical_net_fixing_drc = "true"
mentor_bidirect_value = "INOUT"
mentor_do_path = ""
mentor_input_output_property_name = "PINTYPE"
mentor_input_value = "IN"
mentor_logic_one_value = "1SF"
mentor_logic_zero_one_property_name = "INIT"
mentor_logic_zero_value = "0SF"
mentor_output_value = "OUT"
mentor_primitive_property_name = "PRIMITIVE"
mentor_primitive_property_value = "MODULE"
mentor_reference_property_name = "COMP"
mentor_search_path = ""
mentor_write_symbols = "true"
mgi_scratch_directory = "designware_generator"
multi_pass_test_generation = "false"
pla_read_create_flip_flop = "false"
plot_box = "false"
plot_command = "lpr -Plw"
plot_orientation = "best_fit"
plot_scale_factor = 100
plotter_maxx = 584
plotter_maxy = 764
plotter_minx = 28
plotter_miny = 28
port_complement_naming_style = "%s_BAR"
power_do_not_size_icg_cells = "false"
power_hdlc_do_not_split_cg_cells = "false"
power_keep_license_after_power_commands = "false"
power_preserve_rtl_hier_names = "false"
power_rtl_saif_file = "power_rtl.saif"
power_sdpd_saif_file = "power_sdpd.saif"
read_db_lib_warnings = "FALSE"
read_name_mapping_nowarn_libraries = {}
read_translate_msff = "TRUE"
reoptimize_design_changed_list_file_name = ""
rtl_load_resistance_factor = 0.000000
sdfin_fall_cell_delay_type = "maximum"
sdfin_fall_net_delay_type = "maximum"
sdfin_min_fall_cell_delay = 0.000000
sdfin_min_fall_net_delay = 0.000000
sdfin_min_rise_cell_delay = 0.000000
sdfin_min_rise_net_delay = 0.000000
sdfin_rise_cell_delay_type = "maximum"
sdfin_rise_net_delay_type = "maximum"
sdfin_top_instance_name = ""
sdfout_allow_non_positive_constraints = "false"
sdfout_min_fall_cell_delay = 0.000000
sdfout_min_fall_net_delay = 0.000000
sdfout_min_rise_cell_delay = 0.000000
sdfout_min_rise_net_delay = 0.000000
sdfout_time_scale = 1.000000
sdfout_top_instance_name = ""
sdfout_write_to_output = "false"
search_path = {".", "/me3/cad/synopsys/2000.05/libraries/syn", "/me3/cad/synopsys/2000.05/dw/sim_ver", "/home/cad/techfiles/msu/scmos/synopsys/syn"}
sh_command_abbrev_mode = "Anywhere"
sh_continue_on_error = "true"
sh_enable_page_mode = "true"
sh_source_uses_search_path = "true"
single_group_per_sheet = "false"
site_info_file = "/me3/cad/synopsys/2000.05/admin/license/site_info"
sort_outputs = "false"
spdm_mode = "false"
suppress_errors = {"PWR-18", "OPT-931", "OPT-932"}
symbol_library = {"msu_scmos.sdb"}
synlib_disable_limited_licenses = "true"
synlib_dont_get_license = {}
synlib_evaluation_mode = "false"
synlib_model_map_effort = "medium"
synlib_optimize_non_cache_elements = "true"
synlib_prefer_ultra_license = "false"
synlib_sequential_module = "default"
synlib_wait_for_design_license = {}
syntax_check_status = "false"
synthetic_library = {}
target_library = {"msu_scmos.db"}
tdlout_upcase = "true"
template_naming_style = "%s_%p"
template_parameter_style = "%s%d"
template_separator_style = "_"
test_allow_clock_reconvergence = "true"
test_bsd_allow_tolerable_violations = "false"
test_bsd_control_cell_drive_limit = 0
test_bsd_manufacturer_id = 0
test_bsd_optimize_control_cell = "false"
test_bsd_part_number = 0
test_bsd_version_number = 0
test_bsdl_default_suffix_name = "bsdl"
test_bsdl_max_line_length = 80
test_capture_clock_skew = "small_skew"
test_cc_ir_masked_bits = 0
test_cc_ir_value_of_masked_bits = 0
test_check_port_changes_in_capture = "true"
test_clock_port_naming_style = "test_c%s"
test_dedicated_subdesign_scan_outs = "true"
test_default_bidir_delay = 55.000000
test_default_client_order = {"autofix", "ramcollar"}
test_default_delay = 5.000000
test_default_min_fault_coverage = 95
test_default_period = 100.000000
test_default_scan_style = "multiplexed_flip_flop"
test_default_strobe = 95.000000
test_default_strobe_width = 0.000000
test_design_analyzer_uses_insert_scan = "true"
test_disable_find_best_scan_out = "false"
test_disconnect_non_functional_so = 1
test_dont_fix_constraint_violations = "false"
test_infer_slave_clock_pulse_after_capture = "infer"
test_isolate_hier_scan_out = 0
test_jump_over_bufs_invs = "true"
test_mode_port_inverted_naming_style = "test_mode_i%s"
test_mode_port_naming_style = "test_mode%s"
test_non_scan_clock_port_naming_style = "test_nsc_%s"
test_point_keep_hierarchy = "true"
test_preview_scan_shows_cell_types = "false"
test_protocol_add_cycle = "true"
test_scan_clock_a_port_naming_style = "test_sca%s"
test_scan_clock_b_port_naming_style = "test_scb%s"
test_scan_clock_port_naming_style = "test_sc%s"
test_scan_enable_inverted_port_naming_style = "test_sei%s"
test_scan_enable_port_naming_style = "test_se%s"
test_scan_in_port_naming_style = "test_si%s%s"
test_scan_link_so_lockup_key = "l"
test_scan_link_wire_key = "w"
test_scan_out_port_naming_style = "test_so%s%s"
test_scan_segment_key = "s"
test_scan_true_key = "t"
test_stil_multiclock_capture_procedures = "false"
test_stil_netlist_format = "db"
test_user_defined_instruction_naming_style = "USER%d"
test_user_test_data_register_naming_style = "UTDR%d"
test_write_four_cycle_stil_protocol = "false"
testsim_print_stats_file = "true"
text_editor_command = "xterm -fn 8x13 -e vi %s &"
text_print_command = "lpr -Plw"
timing_self_loops_no_skew = "false"
true_delay_prove_false_backtrack_limit = 1000
true_delay_prove_true_backtrack_limit = 1000
uniquify_naming_style = "%s_%d"
use_port_name_for_oscs = "true"
verbose_messages = "true"
verilogout_debug_mode = "false"
verilogout_equation = "false"
verilogout_higher_designs_first = "FALSE"
verilogout_ignore_case = "false"
verilogout_include_files = {}
verilogout_levelize = "FALSE"
verilogout_no_negative_index = "FALSE"
verilogout_no_tri = "false"
verilogout_show_unconnected_pins = "FALSE"
verilogout_single_bit = "false"
verilogout_unconnected_prefix = "SYNOPSYS_UNCONNECTED_"
vhdllib_architecture = {"UDSM", "FTSM", "FTGS", "VITAL"}
vhdllib_glitch_handle = "true"
vhdllib_logic_system = "ieee-1164"
vhdllib_logical_name = ""
vhdllib_negative_constraint = "false"
vhdllib_pulse_handle = "use_vhdllib_glitch_handle"
vhdllib_sdf_edge = "FALSE"
vhdllib_tb_compare = 0
vhdllib_tb_x_eq_dontcare = "FALSE"
vhdllib_timing_checks = "true"
vhdllib_timing_mesg = "true"
vhdllib_timing_xgen = "false"
vhdllib_vital_99 = "false"
vhdlout_architecture_name = "SYN_%a_%u"
vhdlout_bit_type = "std_logic"
vhdlout_bit_type_resolved = "TRUE"
vhdlout_bit_vector_type = "std_logic_vector"
vhdlout_conversion_functions = {}
vhdlout_debug_mode = "false"
vhdlout_dont_create_dummy_nets = "FALSE"
vhdlout_dont_write_types = "FALSE"
vhdlout_equations = "FALSE"
vhdlout_follow_vector_direction = "FALSE"
vhdlout_levelize = "FALSE"
vhdlout_one_name = "'1'"
vhdlout_package_naming_style = "CONV_PACK_%d"
vhdlout_preserve_hierarchical_types = "VECTOR"
vhdlout_separate_scan_in = "FALSE"
vhdlout_single_bit = "USER"
vhdlout_synthesis_off = "TRUE"
vhdlout_target_simulator = ""
vhdlout_three_state_name = "'Z'"
vhdlout_three_state_res_func = ""
vhdlout_time_scale = 1.000000
vhdlout_top_configuration_arch_name = "A"
vhdlout_top_configuration_entity_name = "E"
vhdlout_top_configuration_name = "CFG_TB_E"
vhdlout_unknown_name = "'X'"
vhdlout_upcase = "FALSE"
vhdlout_use_packages = {"IEEE.std_logic_1164", "IEEE.std_logic_arith"}
vhdlout_wired_and_res_func = ""
vhdlout_wired_or_res_func = ""
vhdlout_write_architecture = "TRUE"
vhdlout_write_components = "TRUE"
vhdlout_write_entity = "TRUE"
vhdlout_write_top_configuration = "TRUE"
vhdlout_zero_name = "'0'"
view_analyze_file_suffix = {"v", "vhd", "vhdl"}
view_arch_types = {"apollo", "decmips", "hp700", "mips", "necmips", "rs6000", "sgimips", "sonymips", "sun3", "sparc"}
view_background = "black"
view_cache_images = "true"
view_command_log_file = "./view_command.log"
view_command_win_max_lines = 1000
view_dialogs_modal = "true"
view_disable_cursor_warping = "true"
view_disable_error_windows = "false"
view_disable_output = "false"
view_error_window_count = 6
view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"}
view_info_search_cmd = "/me3/cad/synopsys/2000.05/infosearch/scripts/InfoSearch"
view_log_file = ""
view_on_line_doc_cmd = "/me3/cad/synopsys/2000.05/sold"
view_read_file_suffix = {"db", "gdb", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
view_script_submenu_items = {"DA to SGE Transfer", "write_sge"}
view_tools_menu_items = {}
view_use_small_cursor = ""
view_use_x_routines = "true"
view_write_file_suffix = {"gdb", "db", "sdb", "do", "edif", "eqn", "fnc", "lsi", "NET", "neted", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
write_name_mapping_nowarn_libraries = {}
write_name_nets_same_as_ports = "false"
write_test_formats = {"synopsys", "tssi_ascii", "tds", "verilog", "vhdl", "wgl"}
write_test_include_scan_cell_info = "true"
write_test_input_dont_care_value = "X"
write_test_max_cycles = 0
write_test_max_scan_patterns = 0
write_test_pattern_set_naming_style = "TC_Syn_%d"
write_test_round_timing_values = "true"
write_test_scan_check_file_naming_style = "%s_schk.%s"
write_test_vector_file_naming_style = "%s_%d.%s"
x11_set_cursor_background = ""
x11_set_cursor_foreground = ""
x11_set_cursor_number = -1
xnfin_dff_clock_enable_pin_name = "CE"
xnfin_dff_clock_pin_name = "C"
xnfin_dff_data_pin_name = "D"
xnfin_dff_q_pin_name = "Q"
xnfin_dff_reset_pin_name = "RD"
xnfin_dff_set_pin_name = "SD"
xnfin_family = "4000"
xnfin_ignore_pins = "GTS GSR GR"
xnfout_clock_attribute_style = "CLK_ONLY"
xnfout_constraints_per_endpoint = "50"
xnfout_default_time_constraints = "true"
xnfout_library_version = ""
xterm_executable = "xterm"


/* Initial dc_shell Aliases */


alias analyze_scan 	"preview_scan"
alias check_clocks 	"check_timing"
alias compile_inplace_changed_list_file_name 	"reoptimize_design_changed_list_file_name"
alias compile_test 	"insert_test"
alias create_test_vectors 	"create_test_patterns"
alias disable_timing 	"set_disable_timing"
alias dont_touch   	"set_dont_touch"
alias dont_touch_network 	"set_dont_touch_network"
alias dont_use     	"set_dont_use"
alias est_resource_preference 	"estimate_resource_preference"
alias fix_hold     	"set_fix_hold"
alias free         	"remove_design"
alias fsm_minimize 	"minimize_fsm"
alias fsm_reduce   	"reduce_fsm"
alias gen          	"create_schematic"
alias group_bus    	"create_bus"
alias groupvar     	"group_variable"
alias lint         	"check_design"
alias list_duplicate_designs 	"include -quiet ldd_script; dc_shell_status = ldd_return_val "
alias ls           	"sh ls -aC "
alias man          	"help"
alias prefer       	"set_prefer"
alias remove_package 	"echo remove_package command is obsolete: packages are stored on disk not in-memory:"
alias report_attributes 	"report_attribute"
alias report_clock_constraint 	"report_timing -path end -to all_registers(-data_pins)"
alias report_clock_tree 	"report_transitive_fanout -clock_tree"
alias report_clocks 	"report_clock"
alias report_constraints 	"report_constraint"
alias report_register 	"report_timing_requirements;report_clock -skew"
alias report_synthetic 	"report_cell"
alias set_connect_delay 	"set_annotated_delay -net"
alias set_internal_arrival 	"set_arrival"
alias set_internal_load 	"set_load"
alias set_ultra_mode 	"set_ultra_optimization"
alias site_info    	"sh cat site_info_file"
alias ungroup_bus  	"remove_bus"
alias verify       	"compare_design"
alias view_cursor_number 	"x11_set_cursor_number"
alias write_sge    	"include db2sge_script"


/* dc_shell Command Log */ 


read ASM_transmitter.db 
ungroup -flatten -all 
write -format lsi -output "ASM_transmitter.lsi" {"ASM_transmitter.db:ASM_transmitter"} 
quit