VeriLogger Pro simulation log created at Tue Apr 15 13:18:34 2003
Beginning Compile
Beginning Phase I
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\ASM_transmitter.v
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\TwotoOne.v
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\shiftReg.v
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\ramFunc.v
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\gcounter.v
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\crc.v
Compiling source file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\TXFSM.v
Finished Phase I
Entering Phase II...
Compiling auto-generated top level module file: C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\McGuyver\SimulatedDiagramResultTim.v
Finished Phase II
Entering Phase III...
C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\ASM_transmitter.v: L22: warning: Port sizes don't match in port #5 (8 vs 8)
C:\Documents and Settings\alworthc\Desktop\chris Transmitter 4-14-03\ASM_transmitter.v: L23: warning: Port sizes don't match in port #4 (8 vs 8)
Finished Phase III
Highest level modules:   syncad_top
Finding handle to syncad_top.shift_out
Finding handle to syncad_top.tx_rdy
Finding handle to syncad_top.ASM_transmitter.CRC_OUT
Finding handle to syncad_top.ASM_transmitter.m_addr
Compile Complete
Finding handle to syncad_top.shift_out
Finding handle to syncad_top.tx_rdy
.
Running...
0 Errors, 2 Warnings
Compile time = 0.00000, Load time = 0.03100, Execution time = 0.03200

Normal exit