/*	IO DEFINITIONS FOR MC68HC12B32
 *	Copyright (c) 1997 by COSMIC Software
 */
#ifndef _BASE
#define _BASE	0
#endif
#define  _IO(x)	@(_BASE)+(x)
#define uint	unsigned int

volatile char PORTA    _IO(0x00);	/* port A */
volatile char PORTB    _IO(0x01);	/* port B */
volatile char DDRA     _IO(0x02);	/* data direction port A */
volatile char DDRB     _IO(0x03);	/* data direction port B */
volatile char PORTE    _IO(0x08);	/* port E */
volatile char DDRE     _IO(0x09);	/* data direction port E */
volatile char PEAR     _IO(0x0a);	/* port E assignment register */
volatile char MODE     _IO(0x0b);	/* mode register */
volatile char PUCR     _IO(0x0c);	/* pull-up control register */
volatile char RDRIV    _IO(0x0d);	/* reduced drive of I/O lines */

volatile char INITRM   _IO(0x10);	/* RAM mapping register */
volatile char INITRG   _IO(0x11);	/* IO mapping register */
volatile char INITEE   _IO(0x12);	/* EEPROM mapping register */
volatile char MISC     _IO(0x13);	/* mapping control register */
volatile char RTICTL   _IO(0x14);	/* real time interrupt control */
volatile char RTIFLG   _IO(0x15);	/* real time interrupt flag */
volatile char COPCTL   _IO(0x16);	/* COP control register */
volatile char COPRST   _IO(0x17);	/* COP arm/reset */
volatile char ITST0    _IO(0x18);	/* interrupt test 0 */
volatile char ITST1    _IO(0x19);	/* interrupt test 1 */
volatile char ITST2    _IO(0x1a);	/* interrupt test 2 */
volatile char ITST3    _IO(0x1b);	/* interrupt test 3 */
volatile char INTCR    _IO(0x1e);	/* interrupt control */
volatile char HPRIO    _IO(0x1f);	/* highest priority */

volatile char BRKCT0   _IO(0x20);	/* Breakpoint Control 0 */
volatile char BRKCT1   _IO(0x21);	/* Breakpoint Control 1 */
volatile uint BRKA     _IO(0x22);	/* Breakpoint Address */
volatile uint BRKD     _IO(0x24);	/* Breakpoint Data */

volatile char PWCLK    _IO(0x40);	/* PWM Clocks */
volatile char PWPOL    _IO(0x41);	/* PWM Clock Polarity */
volatile char PWEN     _IO(0x42);	/* PWM Enable */
volatile char PWPRES   _IO(0x43);	/* PWM Prescale Counter */
volatile char PWSCAL0  _IO(0x44);	/* PWM Scale 0 */
volatile char PWSCNT0  _IO(0x45);	/* PWM Counter 0 */
volatile char PWSCAL1  _IO(0x46);	/* PWM Scale 1 */
volatile char PWSCNT1  _IO(0x47);	/* PWM Counter 1 */
volatile char PWCNT0   _IO(0x48);	/* PWM Channel Counter 0 */
volatile char PWCNT1   _IO(0x49);	/* PWM Channel Counter 1 */
volatile char PWCNT2   _IO(0x4a);	/* PWM Channel Counter 2 */
volatile char PWCNT3   _IO(0x4b);	/* PWM Channel Counter 3 */
volatile char PWPER0   _IO(0x4c);	/* PWM Channel Period 0 */
volatile char PWPER1   _IO(0x4d);	/* PWM Channel Period 1 */
volatile char PWPER2   _IO(0x4e);	/* PWM Channel Period 2 */
volatile char PWPER3   _IO(0x4f);	/* PWM Channel Period 3 */
volatile char PWDTY0   _IO(0x50);	/* PWM Channel Duty 0 */
volatile char PWDTY1   _IO(0x51);	/* PWM Channel Duty 1 */
volatile char PWDTY2   _IO(0x52);	/* PWM Channel Duty 2 */
volatile char PWDTY3   _IO(0x53);	/* PWM Channel Duty 3 */
volatile char PWCTL    _IO(0x54);	/* PWM Control Register */
volatile char PWTST    _IO(0x55);	/* PWM Test Register */
volatile char PORTP    _IO(0x56);	/* port P */
volatile char DDRP     _IO(0x57);	/* data direction port P */

volatile char ATDCTL0  _IO(0x60);	/* A/D control register 0 */
volatile char ATDCTL1  _IO(0x61);	/* A/D control register 1 */
volatile char ATDCTL2  _IO(0x62);	/* A/D control register 2 */
volatile char ATDCTL3  _IO(0x63);	/* A/D control register 3 */
volatile char ATDCTL4  _IO(0x64);	/* A/D control register 4 */
volatile char ATDCTL5  _IO(0x65);	/* A/D control register 5 */
volatile uint ATDSTAT  _IO(0x66);	/* A/D status register */
volatile uint ATDTEST  _IO(0x68);	/* A/D test register */
volatile char PORTAD   _IO(0x6f);	/* port AD data input register */
volatile char ADR0H    _IO(0x70);	/* A/D result 0 */
volatile char ADR1H    _IO(0x72);	/* A/D result 1 */
volatile char ADR2H    _IO(0x74);	/* A/D result 2 */
volatile char ADR3H    _IO(0x76);	/* A/D result 3 */
volatile char ADR4H    _IO(0x78);	/* A/D result 4 */
volatile char ADR5H    _IO(0x7a);	/* A/D result 5 */
volatile char ADR6H    _IO(0x7c);	/* A/D result 6 */
volatile char ADR7H    _IO(0x7e);	/* A/D result 7 */

volatile char TIOS     _IO(0x80);	/* time select */
volatile char CFORC    _IO(0x81);	/* compare force */
volatile char OC7M     _IO(0x82);	/* oc7 mask */
volatile char OC7D     _IO(0x83);	/* oc7 data */
volatile uint TCNT     _IO(0x84);	/* timer counter */
volatile char TSCR     _IO(0x86);	/* timer system control */
volatile char TQCR     _IO(0x87);	/* timer queue control */
volatile char TCTL1    _IO(0x88);	/* timer control 1 */
volatile char TCTL2    _IO(0x89);	/* timer control 2 */
volatile char TCTL3    _IO(0x8a);	/* timer control 3 */
volatile char TCTL4    _IO(0x8b);	/* timer control 4 */
volatile char TMSK1    _IO(0x8c);	/* timer interrupt mask 1 */
volatile char TMSK2    _IO(0x8d);	/* timer interrupt mask 2 */
volatile char TFLG1    _IO(0x8e);	/* timer interrupt flag 1 */
volatile char TFLG2    _IO(0x8f);	/* timer interrupt flag 2 */
volatile uint TC0      _IO(0x90);	/* timer capture/compare 0 */
volatile uint TC1      _IO(0x92);	/* timer capture/compare 1 */
volatile uint TC2      _IO(0x94);	/* timer capture/compare 2 */
volatile uint TC3      _IO(0x96);	/* timer capture/compare 3 */
volatile uint TC4      _IO(0x98);	/* timer capture/compare 4 */
volatile uint TC5      _IO(0x9a);	/* timer capture/compare 5 */
volatile uint TC6      _IO(0x9c);	/* timer capture/compare 6 */
volatile uint TC7      _IO(0x9e);	/* timer capture/compare 7 */
volatile char PACTL    _IO(0xa0);	/* pulse accumulator control */
volatile char PAFLG    _IO(0xa1);	/* pulse accumulator flag */
volatile uint PACNT    _IO(0xa2);	/* pulse accumulator count */
volatile char TIMTST   _IO(0xad);	/* timer test register */
volatile char PORTT    _IO(0xae);	/* timer port data */
volatile char DDRT     _IO(0xaf);	/* timer data direction */

volatile char SC0BDH   _IO(0xc0);	/* SCI 0 baud rate high */
volatile char SC0BDL   _IO(0xc1);	/* SCI 0 baud rate low */
volatile char SC0CR1   _IO(0xc2);	/* SCI 0 control register 1 */
volatile char SC0CR2   _IO(0xc3);	/* SCI 0 control register 2 */
volatile char SC0SR1   _IO(0xc4);	/* SCI 0 status register 1 */
volatile char SC0SR2   _IO(0xc5);	/* SCI 0 status register 2 */
volatile char SC0DRH   _IO(0xc6);	/* SCI 0 data register high */
volatile char SC0DRL   _IO(0xc7);	/* SCI 0 data register low */

volatile char SP0CR1   _IO(0xd0);	/* SPI control register 1 */
volatile char SP0CR2   _IO(0xd1);	/* SPI control register 2 */
volatile char SP0BR    _IO(0xd2);	/* SPI baud rate register */
volatile char SP0SR    _IO(0xd3);	/* SPI status register */
volatile char SP0DR    _IO(0xd5);	/* SPI data register */
volatile char PORTS    _IO(0xd6);	/* port S data register */
volatile char DDRS     _IO(0xd7);	/* port S data direction */
volatile char PURDS    _IO(0xdb);	/* port S pull-up */

volatile char EEMCR    _IO(0xf0);	/* eeprom module configuration */
volatile char EEPROT   _IO(0xf1);	/* eeprom block protect */
volatile char EETST    _IO(0xf2);	/* eeprom test register */
volatile char EEPROG   _IO(0xf3);	/* eeprom control register */
volatile char FEELCK   _IO(0xf4);	/* flash lock register */
volatile char FEEMCR   _IO(0xf5);	/* flash module register */
volatile char FEETST   _IO(0xf6);	/* flash test register */
volatile char FEECTL   _IO(0xf7);	/* flash control register */
volatile char BCR1     _IO(0xf8);	/* BDLC control register 1 */
volatile char BSVR     _IO(0xf9);	/* BDLC state vector register */
volatile char BCR2     _IO(0xfa);	/* BDLC control register 2 */
volatile char BDR      _IO(0xfb);	/* BDLC data register */
volatile char BARD     _IO(0xfc);	/* BDLC analog delay */
volatile char DLCSCR   _IO(0xfd);	/* port DLC control register */
volatile char PORTDLC  _IO(0xfe);	/* port DLC data register */
volatile char DDRDLC   _IO(0xff);	/* port DLC direction register */

#undef uint