;Name:  Derek Marston and Pete Susi
;Date:   3/07/03
;Desc:  This program will wait for a Free Token serially on the RxD pin


RAM             EQU     800h;
FLASH           EQU     8000h;
Stack           EQU     01FFh;
StatusReg       EQU     00C4h;
DataReg         EQU     00C7h;
ControlReg1     EQU     00C2h;
ControlReg2     EQU     00C3h;
BaudRateReg     EQU     00C1h;
SCIvector       EQU     0FFD6h;
PortA           EQU     0000h;
DirA            EQU     0002h;

;******************************************************

;     org        0FFFFh
     
;StartAddr:      DW    FLASH

     org        RAM

RecBuff:        DS      20t;



     org        FLASH

main:
     ;lds       #Stack           ; Configure Stack Pointer
     ldaa      #0FFh;
     staa      DirA;
     clr       PortA;           : Set PortA Lo
     bsr       ConfigPort;

     cli                        ; ENABLE the interrupts (Doofus)

loop:
     nop
     bra        loop;


;******************************************************
;Name:          ConfigPort
;Input:         None
;Output:        None
;Destroys:      A
;Description:   Configures port for:
;               Asyncronous serial data
;               8 bit data, no parity, 1 stop bit
;               enable transmitter and receiever

ConfigPort:
     ldaa       #00100000q      ; no loopback
     staa       ControlReg1;
     ldaa       #00101100q      ; enable transmitter and receiver (and RIE)
     staa       ControlReg2

     ldaa       #20h            ; BR divisor
     staa       BaudRateReg

     rts;

;******************************************************
;Name:          TransmitA
;Input:         A = the byte to transmit
;Output:        None
;Destroys:      X
;Description:   Wait until the transmitter is ready (wait until the
;		TDRE bit in the Status Register is 1), then
;		write the contents of A to the Data register.
TransmitA:
      ldx       #StatusReg      ; get status flags
      ldab       StatusReg
      andb       #10000000q     ; Check for ready
      beq        TransmitA      ; Wait until ready

      staa      DataReg
      rts;


;******************************************************
;Name:		ReceiveByte
;Input:		None.
;Output:	A = the Byte that was received.
;Destroys:	A, Y
;Description:	Wait until the receiver has a byte (wait until the
;		RxRDY bit in the same Status Register is 1), then
;		read the byte from the Data register and return
;		from the subroutine with the data in Accumulator A

ReceiveByte:
	ldy 	#StatusReg
	brclr 	0,Y,20h,ReceiveByte		;exit loop if RxRDY
	ldaa	DataReg
	rts


;******************************************************
;Name:		SendFreeToken
;Input:		none.
;Output:	none.
;Destroys:	A, flags
;Description:	Send one free token

SendFreeToken:

	ldaa	#0AAh
	jsr	TransmitA
	ldaa	#0FFh
	jsr	TransmitA
	ldaa	#0AAh
	jsr	TransmitA
	rts


;******************************************************
;Name ReceiveInterrupt
;Input: none
;Output: none
;Destroys: A, X, Flags
;Desc:		Reads in entire token and stores it
;		in the received buffer RecBuff
;		Then it sets the receieved flag RecFlag

ReceiveInterrupt:

; --- Collect Token ----
	ldx	#RecBuff	; Initialize x w/buffer
	clr	PortA           ; Reset Flag              ***** PORT A IS RxFLAG

	bsr	ReceiveByte	; read first byte
	cmpa	#0AAh		; see if it's AA
	bne	RXIdone		; if not, bad token:discarded

	bsr	ReceiveByte	; read second byte
	cmpa	#0FFh		; if not see if free token
	bne	RXIdone		; if not, token invalid

	bsr 	ReceiveByte     ; Token is free?
	cmpa 	#0AAh		; Check ending Byte
	bne	RXIdone		; if not token is invalid

	ldaa	#0FFh		; if so, set free token flag
	staa	PortA           ;                            ***** PORT A IS RxFLAG
        bra	ProcessFreeToken

RXIdone:
        rti

;******************************************************
;Name:		ProcessFreeToken
;Input:		None
;Output:	None
;Destroys:	Flags
;Desc:		Echos a Free Token

ProcessFreeToken:
        ldaa    #0FFh
        staa    PortA
;	clr	PortA		;token received             ***** PORT A IS RxFLAG

;	bsr	SendFreeToken	;pass on free Token
        bra ProcessFreeToken    ;crash here
	rts

;******************************************************
;Name:		InstallInterruptVector
;  NOT A ROUTINE
;
;InstallInterruptVector:

        org SCIvector           ; address for jump vec: FFD6h

SCIVec:  DW      ReceiveInterrupt

;******************************************************